The invention relates to power MOSFETs with low on-resistance used in ICs with a high breakdown voltage which control a high current such as an IC for a switching power supply, an IC for driving the power system of an automobile, and an IC for driving a flat panel display. The invention relates also to the method of manufacturing the semiconductor devices described above.
Recently, portable instruments have been used widely, and intelligent communication technologies have been developed. In association with these trends, power integrated circuits (Ics) which incorporate power metal oxide semiconductor field effect transistors (MOSFETs) have become one of the very important components. The conventional power IC combines a discrete power MOSFET and a control and drive circuit. In contrast, the new power IC developed recently integrates lateral power MOSFETs into a control circuit. It is required for the new power IC to reduce the size, the electric power consumption and the manufacturing costs thereof, and to improve the reliability. To meet these requirements, research and development of lateral power MOSFETs exhibiting a high breakdown voltage and based on the CMOS process has been explored vigorously.
FIG. 22 is a cross sectional view of a conventional lateral power MOSFET for the breakdown voltage of 30 V. Referring now to FIG. 22, the lateral power MOSFET 101 includes a pxe2x88x92-type substrate 10, a pxe2x88x92-type well 11 on pxe2x88x92-type substrate 10, a p+-type diffusion region 16 in a first surface portion of pxe2x88x92-type well 11, an nxe2x88x92-type diffusion region 17 in a second surface portion of pxe2x88x92-type well 11, an nxe2x88x92-type drift region 18 in a third surface portion of pxe2x88x92-type well 11, an n+type diffusion region 19 in the surface portion of nxe2x88x92-type drift region 18, a gate oxide film 12 on pxe2x88x92-type well 11 and nxe2x88x92-type drift region 18, a gate electrode 13 on gate oxide film 12, a source electrode 14 on p+-type diffusion region 16 and n+-type diffusion region 17, and a drain electrode 15 on n+-type diffusion region 19.
The lateral power MOSFET as described above is subject to certain limitations in minimizing the structure thereof for sustaining the punch-through breakdown voltage, since the expanded drains for sustaining the breakdown voltage and the channels are formed in the surface portion of the semiconductor chip. Since drift regions 18 and the channels are formed along the surface of the semiconductor chip, it is difficult to integrate a number of unit devices into a single chip. Since it is difficult to widen the channel width, there is a limitation in reducing the on-resistance per unit area.
Many lateral power MOSFETs have been proposed. xe2x80x9cA 0.35 xcexcm CMOS based smart power technology for 7 V-50 V applicationsxe2x80x9d, V. Parthasarathy et al., Proceedings of ISPSD, (2000), incorporated herein by reference, describes a lateral power MOSFET, the breakdown voltage thereof is 44 V and the on-resistance per unit area thereof is 30 mxcexa9/mm2. The estimated device pitch (the distance between the centers of the source and the drain) of this MOSFET for the 0.35 xcexcm rule is around 3.6 xcexcm. The 0.35 xcexcm rule refers to the fundamental design rule for designing an integrated circuit in which the minimum dimension for the mask pattern is 0.35 xcexcm. However, the device pitch becomes wider with increase of the breakdown voltage, since the dimensions of the drift region become larger.
The MOSFET having a trench structure as shown in FIG. 23 (hereinafter referred to as a xe2x80x9ctrench-type MOSFETxe2x80x9d) facilitates reducing the device pitch to increase the number of unit devices integrated (cf. U.S. Pat. No. 5,122,848 incorporated herein by reference). Referring now to FIG. 23, the conventional trench-type MOSFET 102 includes trenches 21 formed from the surface of a pxe2x88x92-type substrate 20, a gate oxide film 22 covering the inner side walls of each trench 21, a gate electrode 23 on the inner side of gate oxide film 22, an n+-type diffusion region 27 working as a source region in the bottom of trench 21, and an n+-type diffusion region 29 working as a drain region on substrate 20 and around trench 21.
In FIG. 23, a source electrode 24, a drain electrode 25, and an oxide film 26 are shown. The n+-type diffusion region 29 (drain region) on substrate 20 and the upper end portion of gate electrode 23 are at the same level with gate oxide film 22 interposed therebetween. Due to this arrangement, the breakdown voltage of the trench-type MOSFET illustrated in FIG. 23 is up to 10 V. It is difficult for the illustrated trench-type MOSFET to obtain a breakdown voltage of more than 10 V. The pxe2x88x92-type substrate 20 tends to be punched through easily, since pxe2x88x92-type substrate 20 is used as a channel region. Since the resistance of pxe2x88x92-type substrate 20 is high, the potential of pxe2x88x92-type substrate 20 rises when a leakage current flows in pxe2x88x92-type substrate 20. The leakage current flows into source region 27. The leakage current works as a base current of the parasitic transistor formed of source region 27, substrate 20 and drain region 29, sometimes causing secondary breakdown.
The inventors of the present invention have proposed a lateral power MOSFET employing the trench structure as described above (hereinafter referred to as a xe2x80x9ctrench-type lateral power MOSFETxe2x80x9d) in xe2x80x9cA trench lateral power MOSFET using self-aligned trench bottom contact holesxe2x80x9d, IEDM ""97, Digest, pp. 359-362 (1997), incorporated herein by reference. FIG. 24 is a cross sectional view of the conventional trench-type lateral power MOSFET.
Referring now to FIG. 24, the conventional trench-type lateral power MOSFET 103 includes trenches 31 formed from the surface of a pxe2x88x92-type substrate 30, a gate electrode 33 in each trench 31, an n+-type diffusion region 37 working as a source region around trench 31, and an n+-type diffusion region 39 working as a drain region in the bottom of trench 31. The n+-type diffusion region 39 (drain region) is surrounded by an xe2x88x92n-type region 38 (nxe2x88x92-type drain region) surrounding the lower half of trench 31. The nxe2x88x92-type region 38 is surrounded by a pxe2x88x92-type diffusion region 41 working as a p-type mass.
A p+-type diffusion region 42 is around n+-type diffusion region 37 (source region). A p-type base region 43 is below p+-type diffusion region 42 and n+-type diffusion region 37. A thick oxide film 44 is disposed in the lower half of trench 31 to sustain the breakdown voltage of the MOSFET. A source electrode 34, a drain electrode 35, and an oxide film 36 are shown in FIG. 24. The on-resistance per unit area of the trench-type lateral power MOSFET is 80 mxcexa9/mm2, and the breakdown voltage thereof is 80 V. The device pitch is 4 xcexcm, which is about half the device pitch of the conventional lateral power MOSFET, the breakdown voltage thereof is 80 V.
When employing a trench structure for narrowing the device pitch of a lateral power MOSFET, it is preferable for to have a breakdown voltage of, for example, 30 V, which is lower than the above referenced value of 80 V. However, the trench-type lateral power MOSFET described above has a structure suitable for a breakdown voltage of 80 V. Application of the above described structure of the trench-type lateral power MOSFET to the MOSFETs, the breakdown voltage thereof is lower than 80V, poses the following problems. The thickness of the oxide film 44 for a breakdown voltage of less than 80 V is thinner than that of an oxide film for a breakdown voltage of 80 V. If oxide film 44 is not too thick but thick enough to sustain the breakdown voltage lower than 80 V, the dimensions of the MOSFET will be further reduced. If the oxide film 44 having the thickness for the breakdown voltage of 80 V is used in the MOSFET for the breakdown voltage of lower than 80 V, disadvantageous characteristics including high wiring resistance in the periphery of the device will be caused, since the total dimensions of the resulting device is larger than those of the device including oxide film 44, the thickness thereof is optimized.
Since the gate area of the MOSFET which employs oxide film 44 for the breakdown voltage of 80 V is wider than the gate area of the MOSFET which employs oxide film having optimized thickness, high parasitic capacitance and drive loss increase are caused. In manufacturing conventional trench-type lateral power MOSFETs, shallow trenches are formed at first in Retype substrate 30 and, then, deep trenches are dug from the shallow trenches. Therefore, the process for manufacturing the conventional trench-type lateral power MOSFET is complicated, and the throughput for manufacturing the conventional trench-type lateral power MOSFETs is lower.
In view of the foregoing, it would be desirable to provide a semiconductor device including a trench-type lateral power MOSFET with a breakdown voltage of lower than 80 V and manufactured through a process simpler than the process for manufacturing the conventional trench-type lateral power MOSFET, the breakdown voltage thereof is 80 V. In addition, it would be desirable to provide a. semiconductor device including a trench-type lateral power MOSFET with a breakdown voltage of lower than 80 V, the device pitch thereof is narrower than the device pitch in the conventional trench-type lateral power MOSFET, the breakdown voltage thereof is 80 V, and the on-resistance per unit area thereof is lower than the on-resistance per unit area of the conventional trench-type lateral power MOSFET. Still further, it would be desirable to provide a method of manufacturing the semiconductor device including a trench-type lateral power MOSFET with a breakdown voltage of lower than 80 V.
According to the invention, there is provided a trench-type lateral power MOSFET manufactured by forming an nxe2x88x92-type drift region on a pxe2x88x92-type semiconductor substrate, selectively removing a part of the semiconductor substrate and a part of the nxe2x88x92-type drift region to form trenches, forming a gate insulation film of 0.05 xcexcm in thickness in each trench, forming a polycrystalline silicon gate layer on the gate insulation film, forming a pxe2x88x92-type base region and an n+-type source region in the bottom of the trench; and forming an n+-type drain region in the surface portion of the drift region.
In the trench-type lateral power MOSFET according to the invention, the drift region and the channel region, which should be spaced apart from each other for a certain spacing to obtain a high breakdown voltage, are aligned vertically alongside the trench, and the device pitch is determined by the spacing between the centers of the source contact region and the drain contact region. The gate area and the device pitch of the trench-type lateral power MOSFET according to the invention, which does not include any thick oxide film for obtaining a high breakdown voltage, are narrower than those of the conventional trench-type lateral power MOSFET for the breakdown voltage of 80 V, which includes a thick oxide. The method of manufacturing the trench-type lateral power MOSFET according to the invention, which conducts etching for digging the trenches once, is simpler than the method of manufacturing the conventional trench-type lateral power MOSFET for the breakdown voltage of 80 V, which conducts etching for digging the trenches twice.